PhD position (m/f/d) on high-speed mixed signal IC design for sub picosecond jitter TDCs

Swabian Instruments is a rapidly growing high-tech start-up from Stuttgart (Germany) that is developing world leading FPGA based time-to-digital converters (TDCs) with a timing jitter down to 2.7 ps. Among its customers are top research institutions worldwide, such as MIT, NASA, Harvard University, University of Cambridge, University of Oxford, and Max-Planck-Institutes. In 2019 the team was a finalist of Germany’s most important entrepreneur award, the Deutscher Gründerpreis. The University of Stuttgart is constantly ranked among the best universities within electrical engineering in Germany. The Institute of Smart Sensors (IIS) lead by Prof. Jens Anders is positioned notably within the Center for Integrated Quantum Science and Technology (IQST). The IIS specializes on the development of control and measurement electronics with a focus on digital phase-locked-loops (PLL) and time-to-digital converters. All of these traits make Swabian Instruments and the IIS a top-class research employer.

The R&D team at Swabian Instruments aims at casting its unique knowledge in FPGA based TDC design into a cutting edge TDC ASIC and take the lead in terms of timing resolution and linearity. We are looking for outstanding electrical engineers (MSc) to become part of this endeavor as PhD students with us in collaboration with the Institute of Smart Sensors of the University of Stuttgart. We offer you a research position with a challenging mission statement and the possibility to become a key person in Swabian Instruments’ emerging ASIC design team.

Your task

  • Design a TDC ASIC with sub picosecond timing jitter
  • Simulate and research modern tapped-delay-line and Vernier based TDC architectures
  • Evaluate the performance of the fabricated chip and improve the design
  • Generate patents and publications and present your work on international conferences

Your profile

  • MSc in electrical engineering with a distinguished score
  • Above average general understanding of high-speed electronics
  • Excellent insight in analog IC design is a must (thesis or internship)
  • Previous experience with TDCs or PLLs is a plus
  • Self motivated and self learning

What you can expect

  • Collaboration with the world’s top research institutions
  • Being a key person in our emerging ASIC design team
  • An open minded working atmosphere with a flat organization and flexible working hours
  • You will move the boundary of what is possible with modern TDCs
  • Your chip will become a product and will enable our customers to do new science

Are you the one? Contact us by phone or submit your application via email today!

Marlene Pfisterer