Hardware

Output Channels

The Pulse Streamer 8/2 has 8 digital and 2 analog output channels. The electrical characteristics are tabulated below.

Digital Output

Hardware Version 3.xHardware Version <= 2.x

Property	Value
Output into 50 Ω	0 and 2.6 V
Output impedance [1]	~ 13 Ω
Sampling rate	1 GHz
Rise/fall time (20%-80%)	< 300 ps
Minimum pulse width	2 ns
RMS jitter	< 50 ps

Analog Output

Hardware Version 3.xHardware Version 3.1/3.0Hardware Version <= 2.x

Property	Value
Sampling rate	125 MHz
Output into 50 Ω	-1.0 to 1.0 V
Output impedance [1]	~ 2 Ω
Bandwidth (-3db)	50 MHz
Resolution	14 bit
Offset error (into 50 Ohm load)	< 2 mV
Gain error (into 50 Ohm load)	< 1 %
Rise/fall time (20%-80%)	< 7 ns
Step response overshoot (typ.)	25 %
Output settling time (1%)	< 100 ns
Crosstalk (analog)	< -45 dB
Crosstalk (digital)	< -55 dB

Note

[1] (1,2,3,4,5)

The Pulse Streamer expects a 50 Ω termination to avoid reflections. All output voltages imply the 50 Ω load termination. Without termination, you will get a slightly higher output voltages due to the output impedance > 0 Ω.

Trigger Input

The Pulse Streamer 8/2 has one external trigger input, which can be enabled by software. By default, the Pulse Streamer is automatically rearmed after a sequence with a finite number of n_runs has finished. The sequence can be retriggered after the sequence has finished and the retrigger dead-time has passed. Triggers that come early are discarded. Information about how to configure the trigger functionality of the Pulse Streamer can be found in the Running pulse sequences section

Electrical characteristics:

Hardware Version 3.4Hardware Version <= 3.3Hardware Version 2.x

Property	Value
Termination	50 Ω
Max. voltage range (no damage)	-0.3 to 5.3 V
Input voltage range	0 to 5 V
Trigger level	0.5 V
Minimum pulse width (rising/falling) [4]	4 ns
TriggerToData (rising/falling, typ.) [4]	65/66 ns
TriggerToData jitter	±4 ns
Retrigger dead-time [6]	< 50 ns

Note

[4] (1,2)

Measured with a trigger signal amplitude of 0 to 2.6 V

Note

[6] (1,2,3)

The minimum time gap required between the end of the streamed sequence to trigger the next sequence.

TriggerToData

The trigger to data delay depends on the phase of the incoming trigger event relative to the clock of the Pulse Streamer (125 MHz). The trigger to data signal path shows for the default case (internal clock signal) a delay that is equally distributed between 61 and 69 ns as shown in the following figure.

TriggerToData: Trigger signal (bottom) and the data-out signal range (top)

The reason for this distribution is that all output clocks are derived from the Pulse Streamer clock signal (125 MHz). The positive clock edge samples the trigger events which results in an accuracy of 8 ns. This situation is visualized in the following figure.

Pulse Streamer clock signal (top, 125MHz), trigger signal (bottom left) and the data-out signal range (bottom right)

How to avoid the trigger to data jitter

One way to circumvent the TriggerToData jitter is to use the Pulse Streamer as a master device. When the other devices have a lower TriggerToData jitter, this can solve the issue.

Another possibility is to phase-align the the Pulse Streamer clock and the trigger signal.

Synchronization of Trigger and Pulse Streamer clock

The jitter of the TriggerToData can be avoided by phase aligning the trigger signal with the Pulse Streamer clock. You can achieve synchronization by using the external 125 MHz clock input capability of the Pulse Streamer 8/2 (see Using an external clock). All internal clocks related to the Pulse Streamer output stages will be derived from the signal fed to the clock input.

If the external trigger and the clock of the Pulse Streamer 8/2 are phase-aligned, it will lead to a fixed TriggerToData value between 61-69 ns. The exact value depends on the trigger’s phase position and the positive edge of the clock signal as shown in the following figure:

Pulse Streamer clock (top, 125MHz), trigger signal (bottom left) and the data-out signal range (bottom center)

Note

When the trigger is exactly at the position of the sampling clock, the TriggerToData of each trigger will be randomly +0ns or +8ns as illustrated in the figure below:

Clock signal (top), trigger signal (bottom left) at the critical position with dt=0 showing the discrete 8 ns output jitter (bottom right)

When this situation occurs, please shift your signal ideally by half the clock period (4ns), e.g., with a longer or shorter cable on the clock or trigger signal line.

Note

In case you are using 10MHz as an external reference clock for the Pulse Streamer, phase alignment with the 125 MHz is not possible.

External Clock Input

The Pulse Streamer 8/2 has one input that can receive an external 125MHz or 10 MHz reference clock. Further information about how to set the clock source of the Pulse Streamer can be found in the Using an external clock section.

Electrical characteristics:

Hardware Version 3.xHardware Version 2.xHardware Version <= 2.1

Property	Value
Termination	50 Ω
Coupling	AC coupled
Amplitude range	0.2 - 5 Vpp
Accepted frequencies	10 or 125 MHz

Status LEDs

The Pulse Streamer 8/2 has two LEDs showing information about the status of the device and the network connection.

Device status LED:

green	Pulse Streamer successfully booted
blinking green-orange	sequence is streaming
orange	waiting for trigger/retrigger
blue	sequence finished - retrigger disable
blinking blue	no valid license
continuous red	error

Network LED:

red	no configuration/connection
blinking green-red	setting DHCP - no connection
green	setting DHCP - connection found
blinking blue-red	setting static IP - no connection
blue	setting static IP - connection found